1. Field of the Invention
The present invention relates generally to a semiconductor device, and, more particularly, to a semiconductor device having a contact check circuit for checking a contact between a plurality of pads for receiving external signals and a plurality of probes of a semiconductor testing apparatus prior to a test.
2. Description of the Background Art
Conventionally, a burn-in test has been performed for semiconductor devices such as a DRAM (Dynamic Random Access Memory). This test accelerates an early failure by driving a device as a wafer under the severe condition with higher voltage and higher temperature than usual.
In a burn-in test, signals are input from a semiconductor testing apparatus to a semiconductor device through a plurality of probes of the semiconductor testing apparatus in contact with a plurality of pads of the semiconductor device. Burn-in test cannot be properly performed if probes and pads are not in appropriate contact. Thus, a contact check circuit is provided in each semiconductor device in order to check the contact between probes and pads prior to a burn-in test.
FIG. 8 is a schematic diagram showing a configuration of a conventional semiconductor device 50 having a contact check circuit 55. As shown in FIG. 8, semiconductor device 50, formed on a semiconductor wafer (a silicon wafer, for example) includes a ground pad P10, signal pads P11-P14, contact check circuit 55 and an internal circuit 56.
Ground pad P10 receives ground potential GND from outside (semiconductor testing device). Signal pads P11-P14 receive external signals respectively. Contact check circuit 55 includes N-channel MOS transistors 51-54. N-channel MOS transistors 51-54 are connected between each one of signal pads P11-P14 and ground pad 10, respectively, with their gates connected together to ground pad P10. Internal circuit 56 performs a prescribed operation (data writing and data reading in the case of a DRAM) in accordance with the signals externally input through pads P10-P14.
FIG. 9 is a schematic diagram illustrating a method for checking a contact between pads P10-P14 of semiconductor device 50 and probes 60-64 of a semiconductor testing apparatus 70. With reference to FIG. 9, semiconductor testing apparatus 70 includes a relay 71, an ammeter 73, and a direct-current power supply 74. Probe 60 is grounded. Probes 61-64 are connected to switching terminals 72.1-72.4 of relay 71, respectively. A negative potential -V is applied to a common terminal 72.0 of relay 71 through ammeter 73 by direct current power supply 74.
In order to check contact, a negative potential -V is applied to probe 61 by conducting a current between terminal 72.0 and terminal 72.1 of relay 71, for example. Only when pads P10, P11 and probes 60, 61 are in appropriate contact, respectively, N-channel MOS transistor 51 is rendered conductive, causing a current flow into ammeter 73. When pad P10 and probe 60 and/or pad P11 and probe 61 is not in appropriate contact, no current flows into ammeter 73. Thus, a contact check between pads P10, P11 and probes 60, 61 is allowed. Contacts between other pads P12-P14 and other probes 62-64 can be checked in the same manner.
The conventional method for contact check, however, is time-consuming because pad-to-pad checking is required.
Time required for contact check can be reduced by performing contact check of all pads P10-P14 simultaneously. In this case, however, the cost of semiconductor testing apparatus 74 becomes high because it is necessary to provide as many ammeters 73 as pads P11-P14.
In addition, the conventional method of contact check is not suitable for checking a pad of DRAM to which a positive potential such as power supply potential Vcc, or a boosted potential Vpp is applied, because. in this method a negative potential -V is applied to a pad to be checked. Generally, when a CMOS inverter, for example, exists in a chip circuit, a pad for power supply potential Vcc is connected to an N-well, too. In a P-type silicon substrate, a level of an N-well possibly be lower than a level of P-type silicon substrate, if a pad for power supply potential Vcc attains a negative potential. In such a case, a heavy current caused by a forward-biased PN junction destroys internal circuit 56.